1. Field of the Invention
The present invention relates to the improvement of the semiconductor device having the electrostatic discharge (hereinafter referred to as xe2x80x9cESDxe2x80x9d) resistance of an ESD protection element that protect an internal circuit from the breakdown due to an ESD.
2. Description of the Background Art
An integrated circuit is usually provided with a protection circuit in order to protect an internal circuit from the breakdown due to ESDs, such as discharge of the charge from the exterior, and discharge of the charge charged to the integrated circuit. An ESD protection element that comprises an MOS transistor or a field transistor utilizing a local oxidation of silicon (hereinafter referred to as xe2x80x9cLOCOSxe2x80x9d) oxide film is used as a protection circuit. Generally, one electrode of a transistor serving as an ESD protection element is connected an I/O terminal, and the other electrode is connected to a fixed potential setting terminal, e.g., a ground terminal.
FIG. 25 is a circuit diagram showing a connection example of an NMOS transistor for protection. As shown in FIG. 25, the drain of an NMOS transistor for protection Q1 is connected to an I/O terminal P1, and the source and gate are grounded. An internal circuit (not shown) for performing the actual operation is also connected to the I/O terminal P1.
When the normal voltage is applied to the I/O terminal P1, the NMOS transistor for protection Q1 is in OFF state, causing no influence on the internal circuit. On the other hand, when an ESD occurs and the surge voltage SV is applied to the I/O terminal P1, the PN junction between an N type drain region and a P type well region (substrate) results in breakdown to discharge the surge voltage from the I/O terminal P1 to a ground level (grounding terminal), thereby protecting the internal circuit.
A field transistor has the structure in which an LOCOS oxide film is provided in place of the gate section (i.e., the gate oxide film and gate electrode) of an MOS transistor. Therefore, such a field transistor does not maintain the original transistor structure, but it is called field transistor in the technical fields that deal with ESD. Hereinafter, the regions of a field transistor which correspond to the drain and source regions of an MOS transistor are also referred to as drain and source regions, respectively.
An N type field transistor for protection (whose drain and source regions are of the N type) having the above-mentioned structure may be connected in the same manner as in the NMOS transistor for protection Q1 shown in FIG. 25. However, no potential setting is required for a LOCOS oxide film.
Like the MOS transistor for protection, in the field transistor for protection, no current follows between the drain and source in the normal state, and when an ESD occurs, the PN junction between the N type drain region and the P type well region results in breakdown so that a surge voltage is discharged from an I/O terminal P1 to a ground level (grounding terminal), to protect an internal circuit.
That is, the breakdown of the PN junction of an ESD protection element in the occurrence of an ESD allows the surge voltage to be discharged through the ESD protection element, thereby protecting the internal circuit. In prior art, an ESD protection element has been formed together with an internal circuit on a single semiconductor substrate under the same conditions.
However, as the refinement of elements is advanced, the ESD resistance of an ESD protection element is lowered, and therefore, even if an ESD protection element is formed inside an integrated circuit, failing to protect the breakdown due to an ESD.
According to a first aspect of the present invention, a semiconductor device having an ESD protection element comprises: a semiconductor substrate of a first conductivity type mainly composed of a first material; a first semiconductor region of a second conductivity type, formed in a surface of the semiconductor substrate; a second semiconductor region formed in a surface of the semiconductor substrate, independently of the first semiconductor region, edge portions in the first and second semiconductor regions opposed to each other being defined as first and second edge regions, respectively; and a semiconductor region for ESD protection of the first conductivity type, formed in a region of the semiconductor substrate including at least a region in the vicinity of a junction with the first and second edge portions, the semiconductor region for ESD protection being mainly composed of a second material having a smaller breakdown field than the first material.
According to a second aspect, the semiconductor device having the ESD protection element of the first aspect further comprises: an insulting film on the semiconductor substrate between the first and second semiconductor regions; and a gate electrode on the insulating film.
According to a third aspect, the semiconductor device having the ESD protection element of the first aspect further comprises an isolated insulating region, some of which projects from the semiconductor substrate between the first and second semiconductor regions, and the rest is buried in a surface of the semiconductor substrate.
According to a fourth aspect, the semiconductor device having the ESD protection element of the first aspect is characterized in that the semiconductor region for ESD protection is selectively formed in an upper portion of the semiconductor substrate; and the first edge portion of the first semiconductor region and the second edge portion of the second semiconductor region are formed in the semiconductor region for ESD protection.
According to a fifth aspect, the semiconductor device having the ESD protection element of the fourth aspect is characterized in that the semiconductor region for ESD protection includes first and second partial semiconductor regions for ESD spaced from each other in an upper portion of the semiconductor substrate; and the first edge portion is formed in the first partial semiconductor region for ESD, and the second edge portion is formed in the second partial semiconductor region for ESD.
According to a sixth aspect, the semiconductor device having the ESD protection element of the fourth aspect further comprises a preliminary semiconductor region mainly composed of a specific material, interposed between the semiconductor substrate and the semiconductor region for ESD protection, the specific material containing a mixture of the first material and the second material.
According to a seventh aspect, a method of manufacturing a semiconductor device having an ESD protection element comprises the steps of: (a) preparing a semiconductor substrate of a first conductivity type mainly composed of a first material; (b) selectively forming a semiconductor region for ESD protection mainly composed of a second material, in an upper portion of the semiconductor substrate, the second material having a smaller breakdown field than the first material; and (c) forming first and second semiconductor regions of a second conductivity type independently of each other in a surface of the semiconductor substrate including the semiconductor region for ESD protection, the step (c) forming first and second edge portions opposed to each other in the semiconductor region for ESD protection, the first and second edge portion being edge portions of the first and second semiconductor regions, respectively.
According to an eighth aspect, the method of the seventh aspect is characterized in that: the step (b) includes performing an ion implantation of a specific material having a smaller breakdown field than the first material in an upper portion of the semiconductor substrate, to form the semiconductor region for ESD protection mainly composed of a mixture of the specific material and the first material; and the second material contains the mixture.
According to a ninth aspect of the present invention, in the method of the eighth aspect, the semiconductor region for ESD protection includes first and second partial semiconductor regions for ESD; the step (b) includes the steps of: (b-1) selectively forming a mask portion on the semiconductor substrate; and (b-2) performing an oblique ion implantation of the specific material from above the semiconductor substrate by using the mask portion as a mask, to form the first and second partial semiconductor regions for ESD spaced from each other so as to sandwich an underlying region of the mask region; and the step (c) includes performing a vertical ion implantation of an impurity of a second conductivity type from above the semiconductor substrate by using the mask portion as a mask, to form the first and second semiconductor regions, the first edge portion being formed in the first partial semiconductor region for ESD, the second edge portion being formed in the second partial semiconductor region for ESD.
According to a tenth aspect, in the method of the ninth aspect, step (b-1) includes the steps of: (b-1-1) selectively forming an insulating film on the semiconductor substrate; and (b-1-2) forming a gate electrode on the insulating film; and the mask portion includes the insulated film and the gate electrode.
According to an eleventh aspect, in the method of the seventh aspect, the second material contains a mixture of the first material and a specific material having a smaller breakdown field than the first material; and the step (b) includes the steps of: (b-1) forming a groove in an upper portion of the semiconductor substrate; and (b-2) forming the semiconductor region for ESD protection mainly composed of the second material in the groove by an epitaxial growth of the second material from the semiconductor substrate around the groove.
According to a twelfth aspect, in the method of the seventh aspect, the second material contains a material having a smaller breakdown field than the first material; and the step (b) includes the steps of: (b-1) forming a groove in an upper portion of the semiconductor substrate; (b-2) forming a preliminary semiconductor region mainly composed of a mixture of the first material and the second material along an inner periphery of the groove by an epitaxial growth of the mixture from the semiconductor substrate around the groove; and (b-3) forming a partial semiconductor region for ESD mainly composed of the second material in the groove including the preliminary semiconductor region by an epitaxial growth of the second material from the preliminary semiconductor region.
According to a thirteenth aspect, in the method of the seventh aspect, the step (c) includes the steps of: (c-1) selectively forming an insulating film on the semiconductor substrate; (c-2) forming a gate electrode on the insulating film; and (c-3) forming the first and second semiconductor regions in a surface of the semiconductor substrate bed using portions including the gate electrode, as a mask.
According to a fourteenth aspect, the method of the seventh aspect further comprises step (d), between the steps (a) and (b), of forming an isolated insulating film, some of which projects from the semiconductor substrate, and the rest is buried in a surface of the semiconductor substrate, wherein the step (c) includes forming the first and second semiconductor regions in a surface of the semiconductor substrate by using the isolated insulating film as a mask.
In the semiconductor device having the ESD protection element of the first aspect, a semiconductor region for ESD protection is formed in the region of a semiconductor substrate including at least the region in the vicinity of the junction with the first and second edge portions opposed to each other in first and second semiconductor regions. The semiconductor region for ESD protection is mainly composed of a second material having a smaller breakdown field than a first material which is the principal constituent of the semiconductor substrate.
Therefore, when an ESD occurs and a surge voltage is then applied to the first or second semiconductor region through an I/O terminal, the PN junction of the ESD protection element causes a breakdown to discharge the serge voltage, at a voltage lower than that in the case where the semiconductor region for ESD protection is mainly composed of the first material.
Accordingly, the temperature rise in the occurrence of an ESD is suppressed, leading to an ESD protection element that is resistant to thermal breakdown and excellent in ESD resistance.
An element for use in the normal operation can be formed without degrading its operation characteristics, by forming it in the semiconductor substrate mainly composed of the first material.
The semiconductor device having the ESD protection element of the second aspect has an insulating film formed on the semiconductor substrate between the first and second semiconductor regions, and a gate electrode formed on the insulating film. Thus, for instance, by connecting the first semiconductor region to an I/O terminal and setting the potential between the gate electrode and the second semiconductor region so as not to enter ON state in the normal state, it is possible to obtain an ESD protection element having the MOS transistor structure which causes no influence on another element connected to the I/O terminal in the normal state.
The semiconductor device having the ESD protection element of the third aspect has an isolated insulating region, some of which projects from the semiconductor substrate between the first and second semiconductor region, and the rest is buried in the surface of the semiconductor substrate. Thus, by connecting the first or second semiconductor region to an I/O terminal, it is possible to obtain an ESD protection element having the field transistor structure which always enters OFF state and causes no influence on another element connected to the I/O terminal in the normal state.
In the semiconductor device having the ESD protection element of the fourth aspect, a semiconductor region for ESD protection is selectively formed in the upper portion of a semiconductor substrate. Therefore, it is relatively easy to form an ESD protection element mainly composed of a second material which comprises a mixture of a first material and a specific material, by performing, for example, an ion implantation of the specific material having a smaller breakdown field than the first material, from above the semiconductor substrate.
In the semiconductor device having the ESD protection element of the fifth aspect, the semiconductor region for ESD protection includes a first partial semiconductor region for ESD wherein a first edge portion is present, and a second partial semiconductor region for ESD wherein a second edge portion is present. This enables to obtain an ESD protection element excellent in ESD resistance while minimizing the region for forming the semiconductor region for ESD protection.
The semiconductor device having the ESD protection element of the sixth aspect has a preliminary semiconductor region that is interposed between a semiconductor substrate and the semiconductor region for ESD protection, and is mainly composed of a specific material containing a mixture of first and second materials.
With this structure, it is possible to form a semiconductor region for ESD protection mainly composed of the second material by performing, for example, an epitaxial growth of a specific material (a mixture of the first and second materials) from above the semiconductor substrate, to form a preliminary semiconductor region mainly composed of the specific material, and then performing an epitaxial growth of the second material from the preliminary semiconductor region. This results in the semiconductor region for ESD protection mainly composed of the second material completely different from the first material. Thus, thanks to the semiconductor region for ESD protection mainly composed of the second material having a smaller breakdown field, it is possible to obtain an ESD protection element more excellent in ESD resistance.
In the method of manufacturing a semiconductor device having an ESD protection element according to the seventh aspect, in step (b) a semiconductor region for ESD protection mainly composed of a second material having a smaller breakdown voltage than a first material is selectively formed on the upper portion of a semiconductor substrate, and in step (c) the first and second semiconductor regions of a second conductivity type are formed in the surface of the semiconductor substrate including the semiconductor region for ESD protection. At the same time, first and second edge portions which are the edge portions of the first and second semiconductor regions and face with each other, are formed in the semiconductor region for ESD protection.
Therefore, even when an ESD occurs and a surge voltage is then applied to the first or second semiconductor region through an I/O terminal, the PN junction of the ESD protection element causes a breakdown to discharge the serge voltage, at a voltage lower than that in the case where the semiconductor region for ESD protection is mainly composed of the first material.
As a result, the temperature rise in the occurrence of an ESD is suppressed, leading to an ESD protection element that is resistant to thermal breakdown and excellent in ESD resistance.
In addition, an element for use in the normal operation can be formed without degrading its operation characteristics, by forming it in the semiconductor substrate mainly composed of the first material in other manufacturing step.
In the method of manufacturing a semiconductor device having an ESD protection element according to the eighth aspect, step (b) includes performing an ion implantation of a specific material having a smaller breakdown field than a first material in the upper portion of a semiconductor substrate, to form a semiconductor region for ESD protection mainly composed of a mixture of the first material and a specific material.
Thus, a semiconductor region for ESD protection mainly composed of a second material, which is a mixture of the specific material and the first material, can be obtained with a relatively simple ion implantation processing.
In the method of manufacturing an ESD protection element according to the ninth aspect, in step (b-2), hb using a mask portion selectively formed on the semiconductor substrate as a mask, an oblique rotational ion implantation of a specific material is performed from above a semiconductor substrate, to form first and second partial semiconductor regions for ESD which are isolated by the underlying region of the mask portion.
This enables to obtain an ESD protection element excellent in ESD resistance while minimizing the region for forming the semiconductor region for ESD protection comprising the first and second partial semiconductor regions for ESD.
In the method of manufacturing an ESD protection element according to the tenth aspect, step (b-1) comprises step (b-1-1) of selectively forming an insulating film on a semiconductor substrate, and step (b-1-2) of forming a gate electrode on the insulating film, so that a mask portion includes the insulating film and the gate electrode.
Therefore, it is possible to obtain an ESD protection element having the MOS transistor structure by connecting, for example, a first semiconductor region to an I/O terminal and setting the potential between the gate electrode and a second semiconductor region so as not to enter ON state in the normal state.
In addition, since the insulating film and the gate electrode serve as a mask, the first and second partial semiconductor regions for ESD can be formed in the self alignment manner in the oblique rotational ion implantation of the specific material.
In the method of manufacturing a semiconductor device having an ESD protection element according to the eleventh aspect, in step (b-2) a second material that is a mixture of a first material and a specific material having a smaller breakdown field than the first material, is epitaxially grown from the semiconductor substrate around a groove so that a semiconductor region for ESD protection mainly composed of the second material is formed in the groove. Therefore, a semiconductor region for ESD protection mainly composed of the second material which is a mixture of the specific material and the first material can be obtained by employing epitaxial growth method.
In the method of manufacturing a semiconductor device having an ESD protection element according to the twelfth aspect, in step (b-2) a mixture of first and second materials is epitaxially grown from the semiconductor substrate to form a preliminary semiconductor region mainly composed of the mixture, and in step (b-3) the second material is epitaxially grown from the preliminary semiconductor region to form a partial semiconductor region for ESD mainly composed of the second material. This results in a semiconductor region for ESD protection mainly composed of the second material completely different from the first material. Therefore, thanks to the semiconductor region for ESD protection mainly composed of the second material having a smaller breakdown field, it is possible to obtain an ESD protection element more excellent in ESD resistance.
The method of manufacturing a semiconductor device having an ESD protection element according to the thirteenth aspect, step (c) includes step (c-1) of selectively forming an insulating film on a semiconductor substrate, step (c-2) of forming a gate electrode on the insulating film, and step (c-3) of forming first and second semiconductor regions on the surface of the semiconductor substrate by using the gate electrode as a mask. Therefore, it is possible to obtain an ESD protection element having the MOS transistor structure by connecting, for example, the first semiconductor region to an I/O terminal and setting the potential between the gate electrode and the second semiconductor region so as not to enter ON state in the normal state.
The method of manufacturing a semiconductor device having an ESD protection element according to the fourteenth aspect includes step (d), between steps (a) and (b), of forming an isolated insulating film, some of which projects from a semiconductor substrate, and the rest is buried in the semiconductor substrate. This permits an ESD protection element having the field transistor structure which always enters OFF state in the normal state by connecting, for example, the first semiconductor region to an I/O terminal.
Accordingly, an object of the present invention is to obtain a semiconductor device having an ESD protection element with an improved ESD resistance even when it is formed on a single substrate together with an internal circuit.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.